1. Field
The present disclosure relates to electronic integrated circuits (“ICs”), and more specifically to circuits comprised of stacked transistor devices for switching high frequency signals.
2. Related Art
Most radios, cell phones, TVS, and related equipment today require an “RF switch” to control connections between various transmitter and receiver circuits (“RF” is used generically herein to mean any reasonably high frequency ac signal). FIG. 1 is a simplified schematic diagram of a typical, simple two throw switch that may by used to switch, for example, a single antenna 102 between a transmit signal source 104 and a receive circuit 106. Switches S1 108, S2 110, S3 112 and S4 114 are represented by a mechanical single pole single throw switch symbol. Typically, the switches are controlled such that when S1 is “closed” or conducting at low impedance, S2 is “open” or high impedance. Because no switch is perfect, the node of a transmit/receive switch (such as S1 108 or S2 110) farthest from the antenna is typically shunted to circuit common to reduce the effects of signal leakage through such switch when it is open. Thus, as S2 110 is illustrated in the “open” state, the corresponding shunt switch S4 114 is “closed” to terminate the Receive SRF signal on node 106 to ground 116. Conversely, the shunt switch S3 112 is “open” condition because its corresponding signal switch S1 108 is “closed” to conduct the Transmit SRF signal on node 104 to the antenna 102. To couple the antenna 102 to the receive circuit, the condition of all four switches would typically be inverted to that shown in FIG. 1.
In modern circuits, RF switches such as represented in FIG. 1 are most often implemented using semiconductor devices, typically some form of field effect transistor (FET). Semiconductor RF switches are commonly fabricated using insulated gate FETs, often generically called MOSFETs despite the fact that many do not employ the original metal/oxide/semiconductor construction that gave rise to that acronym. Non-insulating gate FETs, such as junction FETs (JFETs), are also commonly used, particularly with certain semiconductor materials such as GaAs. Each switch may be implemented using a single FET, or, as described herein, a multiplicity of FETs stacked in series.
The impedance of ON (conducting) switches is generally sufficiently low that the voltage developed across it in this condition is negligible. However, switches that are OFF (nonconducting, or high impedance) must typically support the full voltage of the RF signal they control. Thus, the RF power that can be controlled by a semiconductor RF switch depends on its voltage withstand capacity, which in turn depends on the drain-to-source breakdown voltage (BVds) of its constituent transistor(s). In FIG. 1, both S2 110 and S3 112 must withstand the transmit signal voltage SRF with respect to ground.
Integrated circuit fabrication requires many compromises. In particular, many IC transistors that are otherwise highly effective for switching RF signals have a modest BVds, and thus may be inadequate to control signals of substantial amplitude. One solution may be to employ alternative transistor designs yielding higher BVds. However, the tradeoffs necessary to fabricate transistors with higher BVds in an integrated circuit may be burdensome. For example, such design may be incompatible with other circuitry desired for the integrated circuit, or it may otherwise be uneconomical.
Therefore, many semiconductor RF switches today stack a multiplicity of low BVds transistors in series to improve the breakdown performance of the overall switch. FIG. 2 represents an example of such a stacked-transistor semiconductor switch. The switch is disposed between a first node N1 202 and a second node N2 204, and is controlled by a voltage VControl 206. To form the overall switch, a multiplicity j of FETs are “stacked” in series connection, from drain to adjacent source. Thus, a first transistor M1 has a source coupled to N1 202, and a drain coupled directly to the source of a second FET M2 210. Additional FETs, represented by a series of dots, may be similarly connected above M2 210, the drain of the last such intervening FET being coupled to the source of the top or jth FET of the stack, FET Mj 212. Each FET of the stack is controlled by VControl as coupled to the FET's gate via a corresponding gate impedance, such as the base resistances RB1 214, RB1 216, . . . , RBj 218 that are illustrated.
Though the FET channel terminal closer to N1 is referred to as the “source,” and the opposite terminal as the “drain,” this is not a requirement. FETs may be implemented in a wide variety of designs and polarities (e.g., N channel FETs and P channel FETs; enhancement and depletion modes, and various threshold voltages, etc.). Moreover, the circuits in which transistors are employed may be illustrated using different conventions than are followed herein. Transistor polarity and drain-source orientation may often be interchanged without significantly altering the principle of operation of a circuit. Rather than illustrate the numerous possible permutations of drawing conventions, transistor polarities, and transistor designs, it should be well understood by those skilled in the electronics arts that the exemplary description and figures illustrated herein equally represent all such alternative circuit descriptions and equivalent device designs.
For most RF switch purposes, base impedances (represented in FIG. 2 as resistors RBx 214, 216, 218) should combine with the effective corresponding gate capacitance of the FET to form a low-pass filter whose transfer function has at least a single pole roll-off at a frequency that is less than ⅙ the lowest (expected) design frequency for the signal that will exist between N1 and N2. Indeed, the at least one pole frequency is preferably 1/10 such lowest design signal frequency, or even lower. Such low frequency base control permits the gate voltage of each FET to follow the voltage on the channel of the FET, thus assuring the correct “on” or “off” gate/source voltage (Vgs), and also limiting both Vgs and the drain/gate voltage (Vdg) to prevent breakdown of the gate insulation.
Ideally, stacked device switches such as shown in FIG. 2 have a net voltage withstand capacity equal to BVds of the individual FETs, multiplied by the number (j) of FETs in the stack. Thus, a stack of 10 transistors each having BVds of 1.8 V would ideally be capable of switching a signal having a peak amplitude of 18 V. In practice, unfortunately, such stacks may be unable to support such ideal voltage. The voltage withstand capacity can be increased by increasing the number of devices in the stack, but this may cause large increases in the corresponding required integrated circuit area.
For example, assume that BVds for a given fabrication process is 2V (i.e., each single transistor can handle 2V), but that a 16V signal must be controlled. A stack of eight transistors should ideally be able to control a signal of peak amplitude 16V. If eight transistors prove insufficient for this task in practice, then more transistors must be added to support the required voltage. Unfortunately, the series resistance of the stack is the sum of the individual device resistances. Consequently, as the number of stacked devices increases by a factor S, so does the ON resistance of the switch. Therefore, to maintain the required overall ON resistance (or insertion loss), the impedance of each device must be reduced by the factor S. This, in turn, requires that the area of each such device is increased by the factor S. Given S additional FETs, each with an area increased by S, it is clear that the total area of the FETs in the stack will increase as S2. At some point, the switch area can be immense. Moreover, the parasitic capacitances of these transistors typically increase with the area, and this can lead to numerous additional problems.
Thus, there is clearly a need to identify and solve the problem that prevents some stacked FETs from controlling the ideal voltage, i.e., the number of FETs times the BVds of the individual FETs. Embodiments of devices and methods of manufacturing such devices are described herein that can mitigate or eliminate the noted problem, thus enabling stacked transistors to withstand voltages that approach, or even equal, the theoretical maximum for a given BVds of the constituent transistors.